1. Field of the Invention
The present invention generally relates to semiconductor devices. More specifically, the present invention relates to a semiconductor device where a wiring pattern is formed on a semiconductor chip.
2. Description of the Related Art
In recent years, miniaturization, reducing thickness, and reducing weight of semiconductor application products have been drastically progressing for use of digital cameras and various mobile devices such as mobile phones. Because of this, for example, miniaturization and high density are required for a semiconductor device such as NAND type flash memory. A semiconductor device as illustrated in FIG. 1, a so-called CSP (chip size package), for example, has been suggested. The CSP has a substantially same configuration, in planar view, as a semiconductor chip. In addition, a low manufacturing cost, as well as miniaturization and high density, is strongly required in such a semiconductor device.
Here, a related art semiconductor device and its manufacturing method are discussed with reference to FIG. 1 through FIG. 11. FIG. 1 is a cross-sectional view of an example of the related art semiconductor device. As illustrated in FIG. 1, a related art semiconductor device 100 includes a semiconductor chip 101, internal connecting terminals 102, an insulation layer 103, wiring patterns 104, solder resist 106, and external connecting terminals 107.
The semiconductor chip 101 includes a thin plate-shaped semiconductor substrate 109, a semiconductor integrated circuit 111, plural electrode pads 112, and a protection film 113. The semiconductor substrate 109 is formed by, for example, cutting a thin plate-shaped Si wafer into pieces.
The semiconductor integrated circuit 111 is provided on a surface of the semiconductor substrate 109. The semiconductor integrated circuit 111 is formed of a diffusion layer, an insulation layer, a via, wiring and other parts (not illustrated in FIG. 1). The plural electrode pads 112 are provided on the semiconductor integrated circuit 111, and are electrically connected to wirings provided at the semiconductor integrated circuit 111. The protection film 113 is provided on the semiconductor integrated circuit 111. The protection film 113 is configured to protect the semiconductor integrated circuit 111.
The internal connecting terminals 102 are provided on the electrode pads 112. Upper end parts of the internal connecting terminals 102 are exposed from the insulation layer 103 so as to be connected to the wiring patterns 104. The insulation layer 103 is provided so as to cover a surface of the semiconductor chip 101 where the internal connecting terminals 102 are provided. As the insulation layer 103, for example, sheet insulation resin having adhesive properties such as NCF (Non-Conductive Film) or the like can be used.
The wiring patterns 104, which may be so-called re-wirings, are provided so that positions of the electrode pads 112 are different from positions of the external connecting terminals 107. In other words, a so-called fan-in structure for pitch conversion is formed. The wiring patterns 104 are provided on the insulation layer 103. The wiring patterns 104 are connected to the internal connecting terminals 102. The wiring patterns 104 are electrically connected to the electrode pads 112 via the internal connecting terminals 102. The wiring patterns 104 have external connecting terminal providing areas 104A where the external connecting terminals 107 are provided. The solder resist 106 is provided on the insulation layer 103 so as to cover the wiring patterns 104 other than the external connecting terminal providing areas 104A.
The external connecting terminals 107 are provided in the external connecting terminal providing areas 104A of the wiring patterns 104. The external connecting terminals 107 are connected to the wiring patterns 104. As materials of the external connecting terminals 107, for example, an alloy including Pb, an alloy of Sn and Cu, an alloy of Sn and Ag, an alloy of Sn, Ag, and Cu, and other metals and alloys can be used.
FIG. 2 is a plan view of an example of a semiconductor substrate on which is formed the related art semiconductor device. In FIG. 2, a numerical reference 110 denotes a semiconductor substrate. In FIG. 2, “C” represents a position (hereinafter “cutting position C”) where the semiconductor substrate 110 is cut by a dicer. As illustrated in FIG. 2, the semiconductor substrate 110 includes plural semiconductor device forming areas A and scribing areas B where the semiconductor device forming areas A are separated from each other. The semiconductor device forming areas A are where the semiconductor devices 100 are formed. By making the semiconductor substrate 110 have a thin plate-shape configuration and cutting at the cutting positions C, the semiconductor substrates 109 discussed with reference to FIG. 1 are formed.
FIG. 3 through FIG. 11 are first through ninth views showing an example of a manufacturing process of the related art semiconductor device. In FIG. 3 through FIG. 11, parts that are the same as the parts of the related art semiconductor device 100 illustrated in FIG. 1 are given the same reference numerals, and explanation thereof may be omitted. In FIG. 3 through FIG. 11, “A” denotes a semiconductor device forming area (hereinafter “semiconductor device forming area A”). “B” denotes a scribing area B where the semiconductor device forming areas A are separated from each other (hereinafter “scribing area B”). “C” denotes a position (hereinafter “cutting position C”) where the semiconductor substrate 110 is cut by a dicer.
First, in a step illustrated in FIG. 3, a semiconductor chip 101 having the semiconductor integrated circuit 111, plural electrode pads 112, and the protection film 113 is formed at a surface of the semiconductor substrate 111 which is not yet made to have a thin plate-shaped configuration. Next, in a step illustrated in FIG. 4, the internal connecting terminals 102 are formed on the electrode pads 112. In this step, there is unevenness of the heights of the plural internal connecting terminals 102.
Next, in a step illustrated in FIG. 5, a flat plate 115 is pressed onto the plural internal connecting terminals 102 so that the heights of the internal connecting terminals 102 are made even. In other words, a leveling process is performed. Next, in a step illustrated in FIG. 6, the insulation layer 103 made of resin is formed so as to cover the internal connecting terminals 102 and the surface of the semiconductor chip 101 where the internal connecting terminals 102 are formed. As the insulation layer 103, for example, the sheet insulation resin having the adhesive properties such as the NCF (Non-Conductive Film) or the like can be used.
Next, in a step illustrated in FIG. 7, the insulation layer 103 is ground until surfaces 102A of the internal connecting terminals 102 are exposed from the insulation layer 103. At this time, the grinding is performed so that a surface 103A of the insulation layer 103 is made flush with the surfaces 102A of the internal connecting terminals 102. As a result of this, a surface of a structural body illustrated in FIG. 7 (more specifically, the surface 103A of the insulation layer 103 and the surfaces 102A of the internal connecting terminals 102) becomes flat.
Next, in a step illustrated in FIG. 8, the wiring patterns 104 are formed on the flat surface of the structural body illustrated in FIG. 7. More specifically, for example, a metal foil (not illustrated in FIG. 8) is adhered to the structural body illustrated in FIG. 7. Then, resist (not illustrated in FIG. 8) is applied so as to cover the metal foil. Then, by exposing and developing the resist, a resist film (not illustrated in FIG. 8) is formed on the metal foil of a portion corresponding to a forming area of the wiring patterns 104. After that, the metal foil is etched by using the resist film as a mask so that the wiring patterns 104 are formed (subtractive method). Then, the resist film is removed.
Next, in a step illustrated in FIG. 9, the solder resist 106 is formed on the insulation layer 103 so as to cover the wiring patterns 104 situated at a portion other than the external connecting terminal providing areas 104A. Next, in a step illustrated in FIG. 10, the semiconductor substrate 110 is ground from a rear surface side of the semiconductor substrate 110 so that the thin plate-shaped configuration of the semiconductor substrate 110 is made. Next, in a step illustrated in FIG. 11, the external connecting terminals 107 are formed on the external connecting terminal providing areas 104A. Solder bumps, for example, can be used as the external connecting terminals 107. As materials of the external connecting terminals 107, for example, an alloy including Pb, an alloy of Sn and Cu, an alloy of Sn and Ag, an alloy of Sn, Ag, and Cu, and other metals and alloys can be used. After that, parts of the semiconductor substrate 110 are cut at the cutting positions C so that plural semiconductor devices 100 are manufactured.
Thus, according to the related art semiconductor device (chip size package), since the external connecting terminals should be formed on the chip size package, only a so-called a fan-in structure should be applied. See, for example, Japanese Patent Application Publication No. 2001-298149 and Japanese Patent Application Publication No. 2001-217381.
However, as a large number of pins are provided in the semiconductor device, it may become more difficult to arrange re-wirings and therefore a so-called fan-out structure may be required.